Logic-type processing devices, like microcontrollers, generally include a processor, such as a microprocessor, and one or more memories that store programs for execution by the processor. During operation, the processor sequentially executes instructions associated with any one of the programs to, for example, manipulate data, perform calculations, generate various output signals, or otherwise interact with hardware components to perform some predetermined function.
The memories used by processing devices are either read only memories (ROMs), which can be read by the processor but to which the processor cannot write, or random access memories (RAMs), which can be read by the processor and to which the processor can write. While RAMs are more versatile in that they can be easily reprogrammed, RAMs typically have a much larger footprint than ROMs and are more expensive than ROMs. Furthermore, many RAMs are volatile, which means that they must be refreshed on a periodic basis to prevent loss of the information stored therein. As a result, these RAMs are not suitable for storing information, such as programs, which must be retained upon powering-down of the processing device or upon a loss of power to the processing device. For these reasons, ROMs are typically used to store programs that are central or essential to the operation of the logic device.
ROMs can generally be characterized as being erasable or non-erasable. One type of erasable ROM is the erasable programmable read only memory (EPROM) which may be, for example, an electrically-erasable programmable read only memory (EEPROM), an ultraviolet erasable programmable read only memory (UV-EPROM), a flash memory and the like. Non-erasable ROMs, such as masked ROMs or ROMs used in one-time-programmable (OTP) microcontrollers, are either manufactured with the program instructions or data stored therein or are capable of being programmed only once. While erasable ROMs are more versatile than non-erasable ROMs, erasable ROMs are usually much more expensive than non-erasable ROMs.
Due to their versatility, erasable ROMs are typically used during the development of consumer products, such as cellular telephones, having processing devices therein, while the cheaper non-erasable ROMs are used in the final, mass produced product to reduce the cost of the product. In a typical case, a prototype product is provided with a processor and an erasable ROM. A product designer uses a personal computer or workstation to write code for the processing device and, when he or she is satisfied with the code, downloads the code to a device programmer. The device programmer then transfers the code to the erasable ROM, such as an EEPROM, which is then placed within the prototype product. Thereafter, testing of the code within the prototype product is performed and, if necessary, the erasable ROM is erased and reprogrammed multiple times during the development process. When testing is complete, the consumer product is mass produced using non-erasable ROMs having the final version of the designed code burned or otherwise stored therein.
Generally speaking, the mass-produced version of a consumer product, such as a cellular telephone handset, includes one or more application specific integrated circuits (ASICs) or masked microcontrollers therein. ASICs are produced from specifications supplied by a purchaser, and typically have various components like processors, which may be, for example, digital signal processors, RAMs, ROMs and the like formed together in on single integrated circuit. As indicated above, the code used by the processor of the ASIC is typically stored in a masked ROM and, therefore, cannot be changed once the ASIC is manufactured. While there is a significant tooling charge (which may be tens or hundreds of thousands of dollars) associated with the production of an ASIC, the per unit cost of each component can still be very low when high volume production of the ASIC component is needed.
A major drawback associated with the use of an ASIC, a masked microcontroller or any other logic device that stores code in a non-erasable memory is the fact that the code is "hard wired" (not changeable) and thus, must be set at the time the logic device is produced. Because the tooling costs for ASICs are very high, it is undesirable to change the code within the ASIC after production of the ASIC has begun. Accordingly, many hours are typically spent testing code before a logic device that uses a non-erasable memory device to store that code is ordered. However, extensive testing can delay the release of a product using the logic device. Thus, the decision to release code for use in an ASIC comes down to a tradeoff between providing enough time to test the code and getting the ultimate product to market as soon as possible.
Once code is approved and released for use in a product, errors or "bugs" may be found in the released code. In some instances, while no "bugs" may be present within the code, it may be desirable to change some of the parameters of the code or to enhance the operation of the code in some manner. Of course, the decision to correct, optimize, add features or refine the code will result in the need to alter the code. However, making changes in the code within a product that is already released for manufacture requires replacing the non-erasable memories that store the code which, in turn, generates new tooling costs for the manufacture of new ASICs. This activity also delays final release or increases the cost of the product. Furthermore, if changes in the code are needed after the product has been placed on the market, the products which have already been sold may have to be recalled to have the ASICs therein replaced, which can be expensive.
Methods of patching ROM code have been developed to reduce or eliminate the need to replace ROMs within ASICs or other devices. Patching methods disclosed in, for example, Patrick et al., U.S. Pat. No. 4,542,453, Moran, U.S. Pat. No. 4,028,678 and Heene et al., U.S. Pat. No. 4,802,119 detect the ROM address being read by a processor and, if a patch instruction is provided for that ROM address, disable the ROM and enable a patch memory, which then provides a patch instruction for the generated ROM address. Unfortunately, these methods require complex addressing detection and ROM interruption schemes, which necessitate a significant amount of additional hardware. Other patching methods, such as those disclosed in Mizutani et al., U.S. Pat. No. 5,493,674 and EPO document 0 049 353 A1 provide one or more jump instructions within the ROM to be patched and configure each of the jump instructions to cause a jump to a specified location within a patch memory, such as an EPROM. If no patch is to be performed, the patch memory includes a jump instruction back to the ROM. If, however, a patch is to be performed, the patch memory includes a patch program which is executed before jumping back to the ROM. The patching methods disclosed in these documents, however, require an actual jump to the patch memory even when no patch is to be performed and, thus, use at least two jump instructions cycles at each jump location. Furthermore, because these methods cause jumps to predetermined and unchangeable locations within a patch memory, they limit the size of the patch program that can be performed at any particular jump location or otherwise use the patch memory inefficiently.